Jiayi Wang

I design reconfigurable arithmetic units and systolic arrays for AI workloads with diverse numerical formats and matrix shapes. My work spans shared datapaths for mixed-precision computation, native block-scaling support, and flexible arrays for small, non-square GEMMs in LLM serving.

• TransDot — reconfigurable arithmetic: developed a unified FPU supporting FP4/FP8/FP16/FP32 fused multiply-add, subword SIMD, and dot products with FP16/FP32 accumulation, replacing separate per-format FPUs in FPGA AI engines.
• MFSA — multi-format systolic arrays: designed a weight-stationary array with a shared dot-product datapath supporting formats from FP32 to FP4/INT4. Introduced online block-scale rebasing to incorporate MX/NVFP4 scales directly into partial sums and reduce block-scaling overhead.
• piPE-SA — pipelined processing elements: developed timing support for multi-stage PEs in weight- and output-stationary arrays, enabling exploration of PE pipeline depth alongside array size and dataflow.
• Flexible arrays (ongoing): designing a twisted-torus fabric with an orthogonal wavefront to eliminate diagonal data skew and support runtime partitioning into independently scheduled strips, targeting higher utilization on small, non-square GEMMs.

I combine statically scheduled CGRAs with SIMT execution to reduce register-file traffic and instruction-control overhead while preserving the CUDA programming model. This work connects architecture design, compiler development, performance and power modeling, and RTL/FPGA prototyping.

• DICE — GPU architecture: designed a CGRA-based replacement for the SM's SIMD backend, with a Temporal Memory Coalescing Unit for pipelined memory access and swizzled thread-bank mapping to reduce register-file bank conflicts.
• Performance & energy: achieved 1.90× energy efficiency, 42% lower power, and 1.16× performance relative to a modeled NVIDIA Turing SM baseline in GPU-Rodinia evaluation using GPGPU-Sim/GPUWattch. DICE is the subject of a U.S. provisional patent application.
• Compiler & implementation: built a p-graph compiler, contributed to STEP for mapping SIMT kernels onto the spatial fabric, and extended GPGPU-Sim/GPUWattch for evaluation. Led an 8-member RTL team developing the RTL implementation and FPGA prototype for architectural validation.
• CPU integration (ongoing): developing a core-private SIMT engine connected to each CPU core's cache hierarchy, with an in-memory thread-launch mechanism to support fine-grained irregular kernels without driver launches or explicit data transfers.

I develop reusable infrastructure for generating and prototyping CGRAs, enabling architecture exploration through configurable processing elements, interconnects, and control logic.

• RTL generation: built a parameterized Python framework for customizing processing elements, routing networks, and control flow; used across the lab's CGRA projects for architecture exploration and FPGA prototyping.
• Precision-aware communication: investigated how operand precision informs data movement and interconnect design in CGRAs.

I investigate how shared GPU power limits create interference between co-located LLM workloads, and how per-tenant power management can protect latency-sensitive inference.

• Hardware characterization: measured power-induced interference on H100/B200-class GPUs, examining how a co-located workload increases a prioritized tenant's time-to-first-token under a shared power cap.
• Architecture proposal: proposed per-partition power metering and independent per-GPC voltage/frequency control, coordinated by a power arbiter that reallocates budgets at sub-millisecond intervals based on tenant priority, execution phase, and unused capacity.
• Simulation results: evaluated the design using real LLM traces and a serving simulator with power models calibrated on H100 and B200. In simulation, the design restored the prioritized tenant's latency to near its standalone value.

I build multimodal AI agents that analyze classroom video to assess teacher–child interactions and support real-time teacher coaching. VISTA (Video Interaction Scoring & Teaching Assistant) combines video-based assessment with live audio/video analysis.

• VISTA-QEI: developed a video-analysis agent that scores teacher–child interactions using the QEI framework and generates coaching reports grounded in video evidence.
• VISTA-RT: designed a real-time coaching agent integrating live audio/video analysis, rolling context memory, and prioritized prompts delivered through wearable interfaces.
• Prototyping & evaluation: implemented working demos and evaluation tools, and presented prototypes to collaborators in AI and early-childhood education.

I led RTL design and verification for CPHY, a DDR/UCIe-compatible PHY and LPDDR4/4x memory controller, and carried out physical design and SoC integration for a TSMC N28 tape-out.

• Design & verification: led RTL development, mixed-signal integration, and verification of the memory controller and PHY.
• Physical design: performed TSMC N28 physical implementation, including analog/mixed-signal integration, through tape-out.
• SoC integration: integrated the controller and PHY with a RISC-V CPU and a deep-learning accelerator.